The present invention relates to the structure of a MOS (Metal Oxide Semiconductor) type semiconductor device and, more particularly, to the structure of a thin-film MOS transistor on an insulating film.
The structures of conventional polycrystalline silicon thin-film transistors are shown in sectional views of FIGS. 4 and 5.
An oxide film 62 is formed on a silicon substrate 61, and a polycrystalline silicon thin film 63 is deposited on it. The crystallinity, particularly the mean grain size of the polycrystalline silicon thin film 63 has a large effect on transistor characteristics. Therefore, the process is often performed such that amorphous silicon is deposited first and then annealing is performed at a temperature of about 600.degree. C. for a long time to increase the grain size. Thereafter, the polycrystalline silicon thin film 63 is patterned by a photolithographic technique and an ion etching technique, and a gate oxide film 64 is formed on its surface. The formation of the gate oxide film 64 is accomplished by thermally oxidizing the surface of the polycrystalline silicon thin film 63 or by depositing a silicon oxide film by a chemical deposition method. Thereafter, polycrystalline silicon is deposited on the entire surface, and phosphorus, for example, is heavily doped in the polycrystalline silicon by a diffusion method or an ion implantation method. Subsequently, by using the photolithographic technique and the ion etching technique, patterning is performed to form a polycrystalline silicon gate 65. A source region 66 and a drain region 67 are formed in the polycrystalline silicon thin film 63 by ion implantation of arsenic, and this results in a basic structure of a polycrystalline silicon thin-film transistor. The structure shown in FIG. 4 is called a top gate type structure because the gate 65 is present on top of the polycrystalline silicon thin film 63 for forming a conductive channel region.
On the other hand, formation of a polycrystalline silicon gate 73 is performed first, and then a gate oxide film 74 and a polycrystalline silicon thin film 75 are formed in sequence. The result is the structure shown in FIG. 5. In FIG. 5, reference numeral 76 denotes a source region; and 77, a drain region.
In contrast to the structure of FIG. 4, the structure of FIG. 5 is called a bottom gate type structure for the gate 73 is present on the bottom of the polycrystalline silicon thin film 75.
The polycrystalline silicon thin-film transistor is poorer in characteristics than a single-crystal transistor because its conductive channel region consists of polycrystalline silicon. It is said that this degradation in characteristics is primarily caused by grain boundaries in polycrystalline silicon. Increasing the grain size is effective in decreasing the density of the grain boundaries. When the increase in grain size is achieved to a certain extent, however, characteristics, particularly a leakage current in an OFF state, is largely influenced by a distribution of grain boundaries in the p-n junction of a transistor. To decrease the area of the p-n junction is effective, and therefore to reduce a film thickness of the polycrystalline silicon thin film 75 is an effective means to decrease the leakage current. However, the decrease in film thickness of the polycrystalline silicon thin film 75 as a whole introduces problems, for example, reduction in ON current or degradation in subthreshold characteristic.